The present invention relates, in general, to the field of non-volatile, ferroelectric random access integrated circuit ("IC") memory devices. More particularly, the present invention relates to a serial ferroelectric random access memory architecture to equalize column accesses and improve data retention reliability by mitigating undesired imprint, or compensation, effects.
Ferroelectric memory devices, such as the FRAM.RTM. family of solid state, random access memory ("RAM") integrated circuits ("ICs") available from Ramtron International Corporation, Colorado Springs, Colo. provide non-volatile data storage through the use of a ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within the Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles.
A hysteresis curve, wherein the abscissa and ordinate represent the applied voltage and resulting polarization states respectively, may be plotted to represent the response of the polarization of a ferroelectric capacitor to the applied voltage. A more complete description of this characteristic hysteresis curve is disclosed, for example, in U.S. Pat. Nos. 4,914,627 and 4,888,733 assigned to the assignee of the present invention, the disclosures of which are herein specifically incorporated by this reference.
Data stored in a ferroelectric memory cell is "read" by applying an electric field to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce either a logic "1" or "0" at the IC output pins. In a conventional two transistor/two capacitor ("2T/2C") ferroelectric memory cell, a pair of two data storage elements are utilized, each polarized in opposite directions. To "read" the state of a 2T/2C memory cell, both elements are polarized in the same direction and the sense amps measure the difference between the amount of charge transferred from the cells to a pair of complementary bit lines. In either case, since a "read" to a ferroelectric memory is a destructive operation, the correct data is then restored to the cell during a precharge operation.
In a simple "write" operation, an electric field is applied to the cell capacitor to polarize it to the desired state. Briefly, the conventional write mechanism for a 2T/2C memory cell includes inverting the dipoles on one cell capacitor and holding the electrode, or plate, to a positive potential greater than the coercive voltage for a nominal 100 nanosecond ("nsec") time period. The electrode is then brought back to circuit ground for the other cell capacitor to be written for an additional nominal 100 nsec.
However, ferroelectric capacitors tend to be subject to "imprint". That is, they can become "compensated" wherein the hysteresis loop appears to shift to favor the stored state due to a charge build-up. Such imprint can result in an undesirably low signal level being presented to the sense amps upon the performance of subsequent "read" operations, thereby possibly indicating a device failure during test or providing a potentially erroneous indication of stored data. Because of their tendency to imprint, conventional ferroelectric memory devices may be sometimes viewed as perhaps better suited for use as read only memories ("ROMs") than random access memories ("RAMs"). Nevertheless, in many applications, a ferroelectric memory array either is or can be read quite often so a need exists for dealing with imprint characteristics such that its effects can be either reduced or negated their entirety.
Ferroelectric memory devices are generally available as both parallel access (c.f. Ramtron International Corporation FM1208S, FM1608S and FM1808S devices) and serial access (c.f. Ramtron International Corporation FM24C04, FM24C16, FM24164, FM25040 and FM25160 devices) integrated circuit memories. With respect to the latter category, serial memories are not typically accessed randomly because, in order to access one word of data in the device, serial transmission of the access operation code ("opcode" either a "read" or "write") and the word address is required. This means that for two-wire I.sup.2 C (e.g. the FM24C04, FM24C16 and FM24164) and three-wire Serial Peripheral Interface ("SPI" e.g. the FM24164 and FM25040) compliant devices, (wherein both types are typically organized .times.8, that is, one word=one byte) in order to access a single byte of data, it is necessary to transmit two bytes of data in order to read or write a single byte. As a consequence, these serial devices all include an address counter to increment the address so that several bytes of data can be either clocked in or out and only the starting address need be supplied.
As above described, current FRAM memory cell designs require a write back operation after every read (read/restore) because the state of the capacitor in the cell is actually switched to sense the charge and restored at the end of the cycle. The serial memory architecture used currently performs a row access after each address. Therefore, in order to write data to several sequential addresses, the first column will receive the initial write followed by several reinforcing writes (read/restore) while the last address will receive several restores with the old data followed by one write in the new state.